With the ever decreasing geometric size of features contained within semiconductor devices, susceptibility to single event upset (SEU) failure becomes increasingly prominent. In particular, neutron induced SEUs have a greater impact as feature geometries of the semiconductor devices are reduced, since the relative size of the neutron with respect to the semiconductor based feature grows. As such, neutrons that are incident to a silicon nucleus of a semiconductor device within a particular feature may induce an alpha particle to be released by the semiconductor device. Once the alpha particle is released, its ionic polarization may be such that a logic state of the semiconductor device is “flipped”, or reversed.
SEU failures may manifest themselves as soft errors within, for example, a configuration memory cell of a programmable logic device (PLD). In such an instance, the SEU may cause a soft failure, which is to say that the failure may be recoverable by executing a reconfiguration of the PLD's configuration memory. Conversely, however, the SEU may cause a catastrophic failure, in instances where reconfiguration of the configuration memory is not possible, or where some non-recoverable failure has occurred. PLDs, therefore, are particularly prone to SEU failure, since reversal of the logic state of one or more configuration memory cells may render the PLD unusable for its intended purpose.
One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles that may be configured by a group of configuration memory cells. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic that are configured by the logic contained within the corresponding configuration memory cells. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into the configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by the configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Some PLDs, such as the Xilinx Virtex® FPGA, can be further programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration data bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Design mitigation techniques, such as triple redundancy, have been employed within application specific integrated circuits (ASICs) and application specific standard products (ASSPs) to counteract the effects of soft-error based failures. Such mitigation techniques, however, may not be particularly optimal for PLD based applications, since configuration memory cell failures are unique to PLD based applications and, therefore, require the implementation of unique mitigation techniques.
Efforts continue, therefore, to implement soft-error based failure mitigation within integrated circuits such as PLDs that are optimally implemented within PLD based applications.